1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device, and more particularly to a semiconductor device including a buried gate and a method for forming the same.
2. Background of the Invention
A dynamic random access memory (DRAM) device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). The data transfer occurs by using a semiconductor property where an electrical conductivity changes depending on environments. The transistor has three regions, i.e., a gate, a source, and a drain. Electric charges are moved between the source and the drain according to a control signal inputted to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region. The semiconductor property is used in the channel.
In a typical method for manufacturing a transistor, a gate is formed in a semiconductor substrate, and a source and a drain are formed by doping impurities into both sides of the gate. In this case, a channel region of the transistor is defined between the source and the drain under the gate. The transistor having a horizontal channel region occupies a predetermined area of a semiconductor substrate. Therefore, for a given transistor, the number of memory cells may determine the size of the semiconductor device.
If the total area of the semiconductor memory device is reduced, the number of semiconductor memory devices per wafer is increased, thereby improving the productivity. Several methods for reducing the total area of the semiconductor memory device have been proposed. One method is to replace a conventional planar gate having a horizontal channel region by a recess gate in which a recess is formed in a substrate and a channel region is formed along a curved surface of the recess by forming a gate in the recess. Furthermore, a buried gate has been studied which can reduce a parasitic capacitance of a bit line by burying the entire gate within the recess.
FIG. 1 is a cross-sectional view illustrating a method for forming a semiconductor device according to the related art.
Referring to FIG. 1, a trench T for defining a prearranged buried gate region is formed by defining a semiconductor substrate 10 including an active region defined by a device isolation layer. A gate insulating film 12 is formed on the bottom and inner lateral surface of the trench T.
Subsequently, a barrier film 14 and a gate electrode 16 are formed over the gate insulating film 12. The gate electrode 16, the barrier film 14 and the gate insulating film 12 are then etched back so that a buried gate is formed. In general, the barrier film 14 is formed of titanium nitride (TiN), and the gate electrode 16 is formed of tungsten (W). The TiN film acting as the barrier film 14 requires a long period of fabrication time, resulting in low productivity. Since the barrier film 14 and the gate electrode 16 are formed of different metals, it is difficult to simultaneously etch back the barrier film 14 and the gate electrode 16.
Accordingly, in order to simplify a fabrication process, the barrier film 14 and the gate electrode 16 may be formed of the same material, and the fabrication difficulty in etching back the barrier film 14 and the gate electrode 16 can be reduced. However, a material proposed for the barrier film 14 and the gate electrode 16 that are formed of the same material has a disadvantage in that the gate insulating film 12 is deteriorated. Specifically, since the proposed material is high in chlorine (Cl) (e.g., Cl=1.3%), chlorine (Cl) is oxidized by a thermal process so that the gate electrode 16 has higher resistance. Although a typical method which increases a temperature and reduces a deposition time during a thermal process so as to reduce the Cl content has been proposed, a nitridation time required for a process reducing chlorine (Cl) is increased so that the overall process time is increased and it is difficult for the barrier film 14 and the gate electrode 16 to be formed of the same material.